1. Field of the Invention
The present invention relates to a method for fabricating a storage electrode of a semiconductor device.
2. Description of the Prior Art
Recent high integration trend of semiconductor memory devices involves inevitably an abrupt reduction in cell area. In spite of such a reduction in cell area, it is still required to establish a certain capacitance per cell in order to realize an operation of a semiconductor memory device. However, this is very difficult.
In a case of a super-integrated semiconductor device, in particular, a reduction in the capacitance of a capacitor results in an increased soft error caused by alpha (.alpha.) particles.
In the technical field, development of new sophisticated techniques and establishment of reliability of devices have been strongly requisite for the establishment of a capacitance of a predetermine level or above.
For such a requirement, there have been proposed various storage electrode structures, one of which is to provide a rough surface of a capacitor so as to maximize the surface area of the capacitor. In this case, however, a very complex process involving, for example, use of hemispherical polysilicon should be used to obtain the rough surface structure of the capacitor.
Various three-dimensional storage electrode structures have also been proposed to increase the electrode surface area. Of these three-dimensional storage electrode structures, the pin structure has been mainly used because its fabrication is relatively simple. In the case of the pin structure, a certain capacitance may be obtained in spite of a reduced cell area by increasing the number of pins. However, such an increase in number of pins results in an increase in number of process steps because chemical vapor deposition (CVD) oxide films and CVD polysilicon films as conductive layers are repeatedly formed in an alternating manner, correspondingly to the increased number of pins. As a result, there are problems of an increased cost caused by the increase in the number of process steps and a degradation in yield caused by increased particles and increased defects generated due to the frequent use of the CVD process.